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| Features * Functionally and Pin Compatible with the Atmel Rad Hard AT40KAL Series * Ultra High Performance - System Speeds to 85 MHz - Array Multipliers > 45 MHz - 14 ns Flexible SRAM - Internal Tri-state Capability in Each Cell FreeRAMTM - Flexible, Single/Dual Port, Sync/Async 14 ns SRAM - 18432 Bits of Distributed SRAM Independent of Logic Cells for AT40KAL 384 PCI Compliant I/Os - Programmable Output Drive - Fast, Flexible Array Access Facilitates Pin Locking 8 Global Clocks - Fast, Low Skew Clock Distribution - Programmable Rising/Falling Edge Transitions - Distributed Clock Shutdown Capability for Low Power Management - Global Reset/Asynchronous Reset Options - 4 Additional Dedicated PCI Clocks Cache Logic(R) Dynamic Full/Partial Reconfigurability In-System - Unlimited Reprogrammability via Serial or Parallel Modes - Enables Adaptive Designs - Enables Fast Vector Multiplier Updates - Quick-ChangeTM Tools for Fast, Easy Design Changes Package Options - MQFPF160 Industry-standard Design Tools - Seamless Integration (Libraries, Interface, Full Back-annotation) with ExemplarTM, Mentor(R), Synplicity(R) - Timing Driven Placement & Routing - Automatic/Interactive Multi-chip Partitioning - Fast, Efficient Synthesis - Over 75 Automatic Component Generators Create 1000s of Reusable, Fully Deterministic Logic and RAM Functions Intellectual Property Cores - Fir Filters, UARTs, PCI, FFT and Other System Level Functions Easy Migration to Atmel Gate Arrays for High Volume Production Supply Voltage 3.3V Design Tools - ATDH40M: Mother Board - ATDH40D160M: Daughter Board for MQFPF160 - ATDS2100PC: IDS Software Design Kit - ATDH 2225: AT17 Series Configuration Memory ISP Downloadable QML Q Quality Grade * * * Military Reprogrammable FPGAs with FreeRAMTM * AT40KAL Preliminary * * * * * * * Rev. 4263B-AERO-06/03 1 *** Table 1. AT40KAL Device Usable Gates Rows x Columns Cells Registers RAM Bits I/O (max) Note: 1. Packages with FCK will have 8 less clocks. AT40KAL040 40K - 50K 48 x 48 2,304 3,048(1) 18,432 384 Description The AT40KAL is a family of fully PCI-compliant, SRAM-based FPGAs with distributed 14 ns programmable synchronous/asynchronous, dual port/single port SRAM, 8 global clocks, Cache Logic ability (partially or fully reconfigurable without loss of data), automatic component generators, and 50,000 usable gates. I/O counts range from 128 to 384 in Aerospace standard packages and support 3.3V. The AT40KAL is designed to quickly implement high performance, large gate count designs through the use of synthesis and schematic-based tools used on a PC and SunTM platform. Atmel's design tools provide seamless integration with industry standard tools such as Synplicity, Modelsim, Exemplar and Viewlogic. See the IDS datasheet for other supported tools. The AT40KAL can be used as a co-processor for high-speed (DSP/processor-based) designs by implementing a variety of compute-intensive, arithmetic functions. These include adaptive finite impulse response (FIR) filters, Fast Fourier Transforms (FFT), convolvers, interpolators and discrete-cosine transforms (DCT) that are required for video compression and decompression, encryption, convolution and other multimedia applications. The AT40KAL FPGA offers a patented distributed 11 - 13 ns SRAM capability where the RAM can be used without losing logic resources. Multiple independent, synchronous or asynchronous, dual port or single port RAM functions (FIFO, scratch pad, etc.) can be created using Atmel's macro generator tool. The AT40KAL's patented 8-sided core cell with direct horizontal, vertical and diagonal cell-to-cell connections implements ultra fast array multipliers without using any busing resources. The AT40KAL's Cache Logic capability enables a large number of design coefficients and variables to be implemented in a very small amount of silicon, enabling vast improvement in system speed at much lower cost than conventional FPGAs. The AT40KAL is capable of implementing Cache Logic (Dynamic full/partial logic reconfiguration, without loss of data, on-the-fly) for building adaptive logic and systems. As new logic functions are required, they can be loaded into the logic cache without losing the data already there or disrupting the operation of the rest of the chip; replacing or complementing the active logic. The AT40KAL can act as a reconfigurable co-processor. The AT40KAL FPGA family is capable of implementing user-defined, automatically generated, macros in multiple designs; speed and functionality are unaffected by the macro orientation or density of the target device. This enables the fastest, most predictable and efficient FPGA design approach and minimizes design risk by reusing already proven functions. The Automatic Component Generators work seamlessly with industry-stan- Fast, Flexible and Efficient SRAM Fast, Efficient Array and Vector Multipliers Cache Logic Design Automatic Component Generators 2 AT40KAL 4263B-AERO-06/03 AT40KAL dard schematic and synthesis tools to create the fastest, most efficient designs available. The patented AT40KAL series architecture employs a symmetrical grid of small yet powerful cells connected to a flexible busing network. Independently controlled clocks and resets govern every column of cells. The array is surrounded by programmable I/O. Devices offer 50,000 usable gates, and have 3,056 registers. AT40KAL series FPGAs utilize a reliable 0.35 single-poly, 4-metal CMOS process and are 100% factory-tested. Atmel's PC- and workstation-based integrated development system (IDS) is used to create AT40KAL series designs. Multiple design entry methods are supported. The Atmel architecture was developed to provide the highest levels of performance, functional density and design flexibility in an FPGA. The cells in the Atmel array are small, efficient and can implement any pair of Boolean functions of (the same) three inputs or any single Boolean function of four inputs. The cell's small size leads to arrays with large numbers of cells, greatly multiplying the functionality in each cell. A simple, high-speed busing network provides fast, efficient communication over medium and long distances. 3 4263B-AERO-06/03 The Symmetrical Array At the heart of the Atmel architecture is a symmetrical array of identical cells (Figure 1). The array is continuous from one edge to the other, except for bus repeaters spaced every four cells (Figure 2 on page 5). At the intersection of each repeater row and column is a 32 x 4 RAM block accessible by adjacent buses. The RAM can be configured as either a single-ported or dual-ported RAM(1), with either synchronous or asynchronous operation. Note: 1. The right-most column can only be used as single-port RAM. Figure 1. Symmetrical Array Surrounded by I/O (AT40K20) = I/O Pad = AT40K Cell = Repeater Row = Repeater Column = FreeRAM Note: AT40KAL has registered I/Os. Group enable every sector for tri-states on obuf's. 4 AT40KAL 4263B-AERO-06/03 AT40KAL Figure 2. Floorplan (Representative Portion)(1) RV = Vertical Repeater = Horizontal Repeater = Core Cell RH RAM RV RV RV RV RAM RV RV RV RV RAM RV RV RV RV RAM RH RH RH RH RH RH RH RH RH RH RH RH RH RH RH RH RAM RV RV RV RV RAM RV RV RV RV RAM RV RV RV RV RAM RH RH RH RH RH RH RH RH RH RH RH RH RH RH RH RH RAM RV RV RV RV RAM RV RV RV RV RAM RV RV RV RV RAM RH RH RH RH RH RH RH RH RH RH RH RH RH RH RH RH RAM RV RV RV RV RAM RV RV RV RV RAM RV RV RV RV RAM Note: 1. Repeaters regenerate signals and can connect any bus to any other bus (all pathways are legal) on the same plane. Each repeater has connections to two adjacent local-bus segments and two express-bus segments. This is done automatically using the integrated development system (IDS) tool. 5 4263B-AERO-06/03 The Busing Network Figure 3 on page 7 depicts one of five identical busing planes. Each plane has three bus resources: a local-bus resource (the middle bus) and two express-bus (both sides) resources. Bus resources are connected via repeaters. Each repeater has connections to two adjacent local-bus segments and two express-bus segments. Each local-bus segment spans four cells and connects to consecutive repeaters. Each express-bus segment spans eight cells and "leapfrogs" or bypasses a repeater. Repeaters regenerate signals and can connect any bus to any other bus (all pathways are legal) on the same plane. Although not shown, a local bus can bypass a repeater via a programmable pass gate allowing long on-chip tri-state buses to be created. Local/Local turns are implemented through pass gates in the cell-bus interface (see following page). Express/Express turns are implemented through separate pass gates distributed throughout the array. Some of the bus resource on the AT40KAL is used as a dual-function resource. Table 2 shows which buses are used in a dual-function mode and which bus plane is used. The AT40KAL software tools are designed to accommodate dual-function buses in an efficient manner. Table 2. Dual-function Buses Function Cell Output Enable RAM Output Enable RAM Write Enable RAM Address RAM Data In RAM Data Out Clocking Set/Reset Type Local Express Express Express Local Local Express Express Plane(s) 5 2 1 1-5 1 2 4 5 Direction Horizontal and Vertical Vertical Vertical Vertical Horizontal Horizontal Vertical Vertical Bus half length at array edge Bus half length at array edge Bus full length at array edge Bus in first column to left of RAM block Bus full length at array edge Bus in first column to left of RAM block Buses full length at array edge Buses in second column to left of RAM block Comments 6 AT40KAL 4263B-AERO-06/03 AT40KAL Figure 3. Busing Plane (One of Five) = AT40K/40KAL AT40KAL = Local/Local or Express/Express Turn Point = Row Repeater = Column Express Express bus bus Local bus 7 4263B-AERO-06/03 Cell Connections Figure 4(a) depicts direct connections between a cell and its eight nearest neighbors. Figure 4(b) shows the connections between a cell and five horizontal local buses (1 per busing plane) and five vertical local buses (1 per busing plane). Figure 4. Cell Connections CEL CEL CEL plane 5 plane 4 plane 3 plane 2 plane 1 WXYZL W X Y Z L plane 5 plane 4 plane 3 plane 2 plane 1 Horizontal busing plane CEL CEL CEL CEL Vertical busing plane Diagonal direct connect CEL CEL Orthogonal direct connect CEL (a) Cell-to-cell Connections (b) Cell-to-bus Connections 8 AT40KAL 4263B-AERO-06/03 AT40KAL The Cell Figure 5 depicts the AT40KAL cell. Configuration bits for separate muxes and pass gates are independent. All permutations of programmable muxes and pass gates are legal. Vn (V1 - V5) is connected to the vertical local bus in plane n. Hn (H1 - H5) is connected to the horizontal local bus in plane n. A local/local turn in plane n is achieved by turning on the two pass gates connected to Vn and Hn. Pass gates are opened to let signals into the cell from a local bus or to drive a signal out onto a local bus. Signals coming into the logic cell on one local bus plane can be switched onto another plane by opening two of the pass gates. This allows bus signals to switch planes to achieve greater routability. Up to five simultaneous local/local turns are possible. The AT40KAL FPGA core cell is a highly configurable logic block based around two 3input LUTs (8 x 1 ROM), which can be combined to produce one 4-input LUT. This means that any core cell can implement two functions of 3 inputs or one function of 4 inputs. There is a Set/Reset D flip-flop in every cell, the output of which may be tri-stated and fed back internally within the core cell. There is also a 2-to-1 multiplexer in every cell, and an upstream AND gate in the "front end" of the cell. This AND gate is an important feature in the implementation of efficient array multipliers. Figure 5. The Cell "1" NW NE SE SW "1" "1" N E S W X W Y Z FB X W Y 8X1 LUT 8X1 LUT OUT "0" "1" OUT "1" V1 H1 V2 H2 V3 H3 V4 H4 V5 H5 10 Z D Q CLOCK RESET/SET "1" OEH OEV L Pass gates X Y NW NE SE SW N E S W X = Diagonal Direct connect or Bus Y = Orthogonal Direct Connector Bus W = Bus Connection Z = Bus Connection FB = Internal Feed back With this functionality in each core cell, the core cell can be configured in several "modes". The core cell flexibility makes the AT40KAL architecture well suited to most digital design application areas (see Figure 6). 9 4263B-AERO-06/03 Figure 6. Some Single Cell Modes A B C D Synthesis Mode. This mode is particularly important for the use of VHDL design. VHDL Synthesis tools generally will produce as their output large amounts of random logic functions. Having a 4-input LUT structure gives efficient random logic optimization without the delays associated with larger LUT structures. The output of any cell may be registered, tri-stated and/or fed back into a core cell. Arithmetic Mode is frequently used in many designs. As can be seen in the figure, the AT40K core cell can implement a 1-bit full adder (2-input adder with both Carry In and Carry Out) in one core cell. Note that the sum output in this diagram is registered. This output could then be tri-stated and/or fed back into the cell. LUT DQ Q (Registered) and/or Q SUM LUT or DQ A B C LUT SUM (Registered) and/or CARRY LUT DSP/Multiplier Mode. This mode is used to efficiently DQ A B C D PRODUCT (Registered) implement array multipliers. An array multiplier is an array or of bitwise multipliers, each implemented as a full adder PRODUCT and/or LUT with an upstream AND gate. Using this AND gate and the diagonal interconnects between cells, the array multiplier structure fits very well into the AT40K architecture. CARRY DQ Q and/or CARRY IN LUT Counter Mode. Counters are fundamental to almost all digital designs. They are the basis of state machines, timing chains and clock dividers. A counter is essentially an increment by one function (i.e., an adder), with the input being an output (or a decode of an output) from the previous stage. A 1-bit counter can be implemented in one core cell. Again, the output can be registered, tri-stated and/or fed back. LUT CARRY A B C EN Q Tri-state/Mux Mode. This mode is used in many telecommunications applications, where data needs to be routed through more than one possible path. The output of the core cell is very often tri-statable for many inputs to many outputs data switching. 10 AT40KAL 4263B-AERO-06/03 2:1 MUX AT40KAL RAM 32 x 4 dual-ported RAM blocks are dispersed throughout the array as shown in Figure 7. A 4-bit Input Data Bus connects to four horizontal local buses distributed over four sector rows (plane 1). A 4-bit Output Data Bus connects to four horizontal local buses distributed over four sector rows (plane 2). A 5-bit Input Address Bus connects to five vertical express buses in same column. A 5-bit Output Address Bus connects to five vertical express buses in same column. Ain (input address) and Aout (output address) alternate positions in horizontally aligned RAM blocks. For the left-most RAM blocks, Aout is on the left and Ain is on the right. For the right-most RAM blocks, Ain is on the left and Aout is tied off, thus it can only be configured as a single port. For single-ported RAM, Ain is the READ/WRITE address port and Din is the (bi-directional) data port. Right-most RAM blocks can be used only for single-ported memories. WEN and OEN connect to the vertical express buses in the same column. Figure 7. RAM Connections (One Ram Block) CLK CLK CLK CLK Din Ain Dout Aout 32 x 4 RAM CLK WEN OEN Reading and writing of the 11 - 13 ns 32 x 4 dual-port FreeRAM are independent of each other. Reading the 32 x 4 dual-port RAM is completely asynchronous. Latches are transparent; when Load is logic 1, data flows through; when Load is logic 0, data is latched. These latches are used to synchronize Write Adress, Write Enable Not, and Din signals for a synchronous RAM. Each bit in the 32 x 4 dual-port RAM is also a transparent latch. The front-end latch and the memory latch together form an edge-triggered flip flop. When a nibble (bit = 7) is (Write) addressed and LOAD is logic 1 and WE is logic 0, 11 4263B-AERO-06/03 data flows through the bit. When a nibble is not (Write) addressed or LOAD is logic 0 or WE is logic 1, data is latched in the nibble. The two CLOCK muxes are controlled together; they both select CLOCK (for a synchronous RAM) or they both select "1" (for an asynchronous RAM). CLOCK is obtained from the clock for the sector-column immediately to the left and immediately above the RAM block. Writing any value to the RAM clear byte during configuration clears the RAM (see the "AT40KAL/KEL Configuration Series" application note at www.atmel.com). Figure 8. RAM Logic CLOCK "1" 0 1 1 "1" 0 Ain 5 Load Read Address Aout 5 Load Latch Write Address WEN Load 32 x 4 Dual-port RAM Write Enable NOT "1" OE Latch Din 4 Load 4 Din Clear Latch Dout Dout RAM-Clear Byte Figure 9 on page 13 shows an example of a RAM macro constructed using AT40KAL's FreeRAM cells. The macro shown is a 128 x 8 dual-ported asynchronous RAM. Note the very small amount of external logic required to complete the address decoding for the macro. Most of the logic cells (core cells) in the sectors occupied by the RAM will be unused: they can be used for other logic in the design. This logic can be automatically generated using the macro generators. 12 AT40KAL 4263B-AERO-06/03 4263B-AERO-06/03 Figure 9. RAM Example: 128 x 8 Dual-ported RAM (Asynchronous) WE Write Address 2-to-4 Decoder 2-to-4 Decoder Read Address Dout(0) Dout(1) Dout(2) Dout(3) Din(0) Din(1) Din(2) Din(3) Din Ain WEN OEN Dout Aout Din Aout WEN OEN Dout Ain Din Ain WEN OEN Dout Aout Din Aout WEN OEN Dout Ain Din(4) Din(5) Din(6) Din(7) Din Ain WEN OEN Dout Aout Din Aout WEN OEN Dout Ain Din Ain WEN OEN Dout Aout Din Aout WEN OEN Dout Ain Dout(4) Dout(5) Dout(6) Dout(7) Local Buses Express Buses Dedicated Connections AT40KAL 13 Clocking Scheme There are eight Global Clock buses (GCK1 - GCK8) on the AT40KAL FPGA. Each of the eight dedicated Global Clock buses is connected to one of the dual-use Global Clock pins. Any clocks used in the design should use global clocks where possible: this can be done by using Assign Pin Locks to lock the clocks to the Global Clock locations. In addition to the eight Global Clocks, there are four Fast Clocks (FCK1 - FCK4), two per edge column of the array for PCI specification. Even the derived clocks can be routed through the Global network. Access points are provided in the corners of the array to route the derived clocks into the global clock network. The IDS software tools handle derived clocks to global clock connections automatically if used. Each column of an array has a "Column Clock mux" and a "Sector Clock mux". The Column Clock mux is at the top of every column of an array and the Sector Clock mux is at every four cells. The Column Clock mux is selected from one of the eight Global Clock buses. The clock provided to each sector column of four cells is inverted, non-inverted or tied off to "0", using the Sector Clock mux to minimize the power consumption in a sector that has no clocks. The clock can either come from the Column Clock or from the Plane 4 express bus (see Figure 10 on page 15). The extreme-left Column Clock mux has two additional inputs, FCK1 and FCK2, to provide fast clocking to left-side I/Os. The extreme-right Column Clock mux has two additional inputs as well, FCK3 and FCK4, to provide fast clocking to right-side I/Os. The register in each cell is triggered on a rising clock edge by default. Before configuration on power-up, constant "0" is provided to each register's clock pins. After configuration on power-up, the registers either set or reset, depending on the user's choice. The clocking scheme is designed to allow efficient use of multiple clocks with low clock skew, both within a column and across the core cell array. 14 AT40KAL 4263B-AERO-06/03 AT40KAL Figure 10. Clocking (for One Column of Cells) } FCK (2 per Edge Column of the Array) GCK1 - GCK8 Column Clock Mux "1" Sector Clock Mux Global Clock Line (Buried) Express Bus (Plane 4; Half length at edge) "1" Repeater Sector Clock Mux "1" "1" 15 4263B-AERO-06/03 Set/Reset Scheme The AT40KAL family reset scheme is essentially the same as the clock scheme except that there is only one Global Reset. A dedicated Global Set/Reset bus can be driven by any User I/O, except those used for clocking (Global Clocks or Fast Clocks). The automatic placement tool will choose the reset net with the most connections to use the global resources. You can change this by using an RSBUF component in your design to indicate the global reset. Additional resets will use the express bus network. The Global Set/Reset is distributed to each column of the array. Like Sector Clock mux, there is Sector Set/Reset mux at every four cells. Each sector column of four cells is set/reset by a Plane 5 express bus or Global Set/Reset using the Sector Set/Reset mux (Figure 11 on page 17). The set/reset provided to each sector column of four cells is either inverted or non-inverted using the Sector Reset mux. The function of the Set/Reset input of a register is determined by a configuration bit in each cell. The Set/Reset input of a register is active low (logic 0) by default. Setting or Resetting of a register is asynchronous. Before configuration on power-up, a logic 1 (a high) is provided by each register (i.e., all registers are set at power-up). 16 AT40KAL 4263B-AERO-06/03 AT40KAL Figure 11. Set/Reset (for One Column of Cells) Each Cell has a programmable Set or Reset Sector Set/Reset Mux Repeater "1" Global Set/Reset Line (Buried) "1" Express Bus (Plane 5; Half length at edge) "1" "1" Any User I/O can drive Global Set/Reset line 17 4263B-AERO-06/03 I/O Structure Pad AT40KAL has registered I/Os and group enable every sector for tri-states on obuf's. The I/O pad is the one that connects the I/O to the outside world. Note that not all I/Os have pads: the ones without pads are called Unbonded I/Os. The number of unbonded I/Os varies with the device size and package. These unbonded I/Os are used to perform a variety of bus turns at the edge of the array. Each pad has a programmable pull-up and pull-down attached to it. This supplies a weak "1" or "0" level to the pad pin. When all other drivers are off, this control will dictate the signal level of the pad pin. The input stage of each I/O cell has a number of parameters that can be programmed either as properties in schematic entry or in the I/O Pad Attributes editor in IDS. The threshold level is a CMOS-compatible level. A Schmitt trigger circuit can be enabled on the inputs. The Schmitt trigger is a regenerative comparator circuit that adds 1V hysteresis to the input. This effectively improves the rise and fall times (leading and trailing edges) of the incoming signal and can be useful for filtering out noise. The input buffer can be programmed to include four different intrinsic delays as specified in the AC timing characteristics. This feature is useful for meeting data hold requirements for the input signal. The output drive capabilities of each I/O are programmable. They can be set to FAST, MEDIUM or SLOW (using IDS tool). The FAST setting has the highest drive capability (16 mA at 5V) buffer and the fastest slew rate. MEDIUM produces a medium drive (12 mA at 5V) buffer, while SLOW yields a standard (4 mA at 5V) buffer. The output of each I/O can be made tri-state (0, 1 or Z), open source (1 or Z) or open drain (0 or Z) by programming an I/O's Source Selection mux. Of course, the output can be normal (0 or 1), as well. The Source Selection mux selects the source for the output signal of an I/O. See Figure 12 on page 21. The AT40KAL has three kinds of I/Os: Primary I/O, Secondary I/O and a Corner I/O. Every edge cell except corner cells on the AT40KAL has access to one Primary I/O and two Secondary I/Os. Every logic cell at the edge of the FPGA array has a direct orthogonal connection to and from a Primary I/O cell. The Primary I/O interfaces directly to its adjacent core cell. It also connects into the repeaters on the row immediately above and below the adjacent core cell. In addition, each Primary I/O also connects into the busing network of the three nearest edge cells. This is an extremely powerful feature, as it provides logic cells toward the center of the array with fast access to I/Os via local and express buses. It can be seen from the diagram that a given Primary I/O can be accessed from any logic cell on three separate rows or columns of the FPGA. See Figures 12a and 13a. Every logic cell at the edge of the FPGA array has two direct diagonal connections to a Secondary I/O cell. The Secondary I/O is located between core cell locations. This I/O Pull-up/Pull-down CMOS Schmitt Delays Drive Tri-State Source Selection Mux Primary, Secondary and Corner I/Os Primary I/O Secondary I/O 18 AT40KAL 4263B-AERO-06/03 AT40KAL connects on the diagonal inputs to the cell above and the cell below. It also connects to the repeater of the cell above and below. In addition, each Secondary I/O also connects into the busing network of the two nearest edge cells. This is an extremely powerful feature, as it provides logic cells toward the center of the array with fast access to I/Os via local and express buses. It can be seen from the diagram that a given Secondary I/O can be accessed from any logic cell on two rows or columns of the FPGA. See Figure 12a and Figure 13b. Corner I/O Logic cells at the corner of the FPGA array have direct-connect access to five separate I/Os: 2 Primary, 2 Secondary and 1 Corner I/O. Corner I/Os are like an extra Secondary I/O at each corner of the array. With the inclusion of Corner I/Os, an AT40KAL FPGA with n x n core cells always has 8n I/Os. As the diagram shows, Corner I/Os can be accessed both from the corner logic cell and the horizontal and vertical busing networks running along the edges of the array. This means that many different edge logic cells can access the Corner I/Os. See Figure 14. 19 4263B-AERO-06/03 Figure 12. South I/O (Mirrored for North I/O) TRI-STATE CELL "0" "1" VCC DRIVE PULL-UP "0" PAD "1" CELL PULL-DOWN SOURCE SELECT MUX TTL/CMOS SCHMITT GND DELAY (a)(a) Primary I/O Primary I/O CELL TRI-STATE "0" "1" CELL VCC DRIVE PULL-UP "0" "1" PAD PULL-DOWN SOURCE SELECT MUX TTL/CMOS SCHMITT GND DELAY CELL (b) Secondary I/O 20 AT40KAL 4263B-AERO-06/03 AT40KAL Figure 13. West I/O (Mirrored for East I/O) a. Primary I/0 TRI-STATE "0" "1" VCC PULL-UP "0" DRIVE CELL "1" PAD RST PULL-DOWN TTL/CMOS GND SCHMITT DELAY OCLK ICLK RST CELL b. Secondary I/O 21 4263B-AERO-06/03 Figure 14. Northwest Corner I/O (Similar NE/SE/SW Corners) PULL-DOWN PULL-UP PAD PAD VCC VCC GND TTL/CMOS SCHMITT DELAY ICLK RST OCLK OCLK RST RST RST PULL-DOWN PULL-UP GND TTL/CMOS SCHMITT DELAY ICLK RST DRIVE TRI-ST ATE DRIVE TRI-ST ATE "0" "1" "0" "1" "0" "1" "0" TRI-STATE "0" "1" VCC PULL-UP DRIVE "0" OCLK RST PAD "1" CELL CELL PULL-DOWN TTL/CMOS SCHMITT DELAY GND ICLK RST "1" CELL 22 AT40KAL 4263B-AERO-06/03 AT40KAL Electrical Characteristics Absolute Maximum Ratings* Operating Temperature.................................. -55C to +125C Storage Temperature ..................................... -65 C to +150C Junction Temperature .................................................. +150C Voltage on Any Pin with Respect to Ground (1) ..........................-0.5V to VCC +0.5V Supply Voltage (VCC) ................................................ 5V 10% ESD (RZAP = 1.5K, CZAP = 100 pF)................................. 4000V 1. For DC Input Voltage (VI) Minimum voltage of -0.5V DC, which may undershoot to -2.0V for pulses of less than 20 ns. *Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability. DC and AC Operating Range Operating Temperature VCC Power Supply Input Voltage Level (CMOS) High (VIHC) Low (VILC) -55C to +125C 3.3V 0.3V 70% - 100% VCC 0 - 30% VCC 23 4263B-AERO-06/03 DC Characteristics Symbol VIH VIL Parameter High-level Input Voltage Low-level Input Voltage Conditions CMOS TTL CMOS TTL IOH = 4 mA VCC = VCC min VOH High-level Output Voltage IOH = 12 mA VCC = 3.0V IOH = 16 mA VCC = 3.0V IOL = -4 mA VCC = 3.0V VOL Low-level Output Voltage IOL = -12 mA VCC = 3.0V IOL = -16 mA VCC = 3.0V IIH IIL High-level Input Current Low-level Input Current High-level Tri-state Output Leakage Current Low-level Tri-state Output Leakage Current Standby Current Consumption Input Capacitance VIN = VCC max With pull-down, VIN = VCC VIN = VSS With pull-up, VIN = VSS Without pull-down, VIN = VCC max With pull-down, VIN = VCC max Without pull-up, VIN = VSS With pull-up, VIN = VSS for CON Standby, unprogrammed All pins -5 20 -5 -300.0 -5 20 -5 -500 -150.0 1 -50 75 Min 70% VCC 2.0 -0.3 -0.3 2.4 2.4 2.4 0.4 0.4 0.4 5 300.0 5 -20 5 300.0 5 -110 5 10.0 30% VCC 0.8 Typ Max Units V V V V V V V V V V A A A A A A mA IOZH IOZL ICC CIN Note: A mA pF 1. Parameter based on characterization and simulation; it is not tested in production. Power-On Power Supply Requirements Atmel FPGAs require a minimum rated power supply current capacity to ensure proper initialization, and the power supply ramp-up time does not affect the current required. A fast ramp-up time requires more current than a slow ramp-up time. Table 3. Power-on Supply Requirements Description Maximum Current(1)(2) Maximum Current Supply Note: 100 mA 1. Devices are guaranteed to initialize properly at 50% of the minimum current listed above. A larger capacity power supply may result in a larger initiallization current. 2. Ramp-up time is measured from 0V DC to 3.6V DC. Peak current required lasts less than 2 ms, and occurs near the internal power on reset threshold voltage. 24 AT40KAL 4263B-AERO-06/03 AT40KAL AC Timing Characteristics Delays are based on fixed loads and are described in the notes. Maximum times based on worst case: Vcc = 3.0V, temperature = 125C. Minimum times based on best case: Vcc = 3.60V, temperature = -55C. Maximum delays are the average of tPDLH and tPDHL. Cell Function Core 2-input gate 3-input gate 3-input gate 4-input gate Fast carry Fast carry Fast crry Fast carry Fast carry Fast carry Fast carry Fast carry DFF DFF DFF DFF Incremental -> L Local output enable Local output enable tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPZX (max) tPXZ (max) x/y -> x/y x/y/z -> x/y x/y/w -> x/y x/y/w/z -> x/y y -> y x -> y y -> x x -> x w -> y w -> x z -> y z -> x clk -> x/y R -> x/y S -> x/y q -> w x/y -> L oe -> L oe -> L 1.9 2.3 2.5 2.5 1.8 1.7 1.8 1.9 2.4 2.5 2.3 2.3 2.1 2.8 2.9 2.2 1.7 1.5 0.8 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load Parameter Path AT40KAL Units Notes AC Timing Characteristics All input I/O characteristics measured from VIH of 50% of VDD at the pad (CMOS threshold) to the internal VIH of 50% of VDD. All output I/O characteristics are measured as the average of tPDLH and tPDHL to the pad VIH of 50% of VDD. Cell Function Repeaters Repeater Repeater Repeater Repeater Repeater Repeater tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) L -> E E -> E L -> L E -> L E -> IO L -> IO 1.2 1.2 1.2 1.2 0.5 0.5 ns ns ns ns ns ns 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load 1 unit load Parameter Path AT40KAL Units Notes 25 4263B-AERO-06/03 Cell Function I/O Input Input Input Input Output, slow Output, medium Output, fast Output, slow Output, slow Output, medium Output, medium Output, fast Output, fast Parameter Path AT40KAL Units Notes tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPZX (max) tPXZ (max) tPZX (max) tPXZ (max) tPZX (max) tPXZ (max) pad -> x/y pad -> x/y pad -> x/y pad -> x/y x/y/E/L -> pad x/y/E/L -> pad x/y/E/L -> pad oe -> pad oe -> pad oe -> pad oe -> pad oe -> pad oe -> pad 2.7 4.9 8.1 11.3 11.2 8.4 6.9 12.2 1.9 7.8 3.3 6.1 3.3 ns ns ns ns ns ns ns ns ns ns ns ns ns no extra delay 1 extra delay 2 extra delays 3 extra delays 50 pf load 50 pf load 50 pf load 50 pf load 50 pf load 50 pf load 50 pf load 50 pf load 50 pf load 26 AT40KAL 4263B-AERO-06/03 AT40KAL AC Timing Characteristics Clocks and Reset Input buffers are measured from a VIH of 1.5V at the input pad to the internal VIH of 50% of VCC. Maximum times for clock input buffers and internal drivers are measured for rising edge delays only. Cell Function GCK Input buffer FCK Input buffer Clock column driver Clock sector driver GSRN Input buffer Global clock to output Parameter tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) tPD (max) Path pad -> clock pad -> clock clock -> colclk colclk -> secclk colclk -> secclk clock pad -> out Device AT40KAL AT40KAL AT40KALAT 40KAL AT40KAL AT40KAL AT40KAL 2.5 1.9 1.1 0.7 7.2 13.4 Units ns ns ns ns ns ns rising edge clock fully loaded clock tree rising edge DFF 20 mA output buffer 50 pf pin load rising edge clock fully loaded clock tree rising edge DFF 20 mA output buffer 50 pf pin load Notes rising edge clock rising edge clock rising edge clock rising edge clock Global Clocks and Set/Reset Fast clock to output tPD (max) clock pad -> out AT40KAL 12.4 ns Notes: 1. 2. 3. 4. CMOS buffer delays are measured from a VIH of 1/2 VCC at the pad to the internal VIH at A. The input buffer load is constant. Buffer delay is to a pad voltage of 1.5V with one output switching. Parameter based on characterization and simulation; not tested in production. Exact power calculation is available in Atmel FPGA Designer software. 27 4263B-AERO-06/03 AC Timing Characteristics Cell Function Async RAM Write Write Write Write Write Write Write Write Write/Read Read Read Read Sync RAM Write Write Write Write Write Write Write Write Write Write/Read Write/Read Read Read Read tCYC (min) tCLKL (min) tCLKH (min) tsetup (min) thold (min) tsetup (min) thold (min) tsetup (min) thold (min) tPD (max) tPD (max) tPD (max) tPZX (max) tPXZ (max) cycle time clk clk we setup -> clk we hold -> clk wr addr setup -> clk wr addr hold -> clk wr data setup -> clk wr data hold -> clk din -> dout clk -> dout rd addr -> dout oe -> dout oe -> dout 14 5.5 5.5 3.5 0.0 5.5 0.0 4.3 0.0 7.0 4.9 4.8 3.3 3.3 ns ns ns ns ns ns ns ns ns ns ns ns ns ns rd addr = wr addr rd addr = wr addr pulse width low pulse width high tWECYC (min) tWEL (min) tWEH (min) tsetup (min) thold (min) tsetup (min) thold (min) thold (min) tPD (max) tPD (max) tPZX (max) tPXZ (max) cycle time we we wr addr setup -> we wr addr hold -> we din setup -> we din hold -> we oe hold -> we din -> dout rd addr -> dout oe -> dout oe -> dout 14 5.5 5.5 5.8 0.0 5.0 0.0 0.0 7.0 4.8 3.3 3.3 ns ns ns ns ns ns ns ns ns ns ns ns rd addr = wr addr pulse width low pulse width high Parameter Path AT40KAL Units Notes 28 AT40KAL 4263B-AERO-06/03 AT40KAL FreeRAM Asynchronous Timing Characteristics Single Port Write/Read tCLKH CLK tWCS WE tACS ADDR 0 1 tWCH tACH 2 3 OE tOXZ DATA tDCS tDCH tOZX tAD Dual Port Write with Read tCYC tCLKH CLK tWCS WE tACS WR ADDR 0 1 tCLKL tWCH tACH 2 tDCS WR DATA tDCH RD ADDR = WR ADDR 1 tCD RD DATA Dual Port Read RD ADDR 0 1 OE tOZX tAD tOXZ DATA 29 4263B-AERO-06/03 FreeRAM Synchronous Timing Characteristics Single Port Write/Read tCLKH CLK tWCS WE tACS ADDR 0 1 tWCH tACH 2 3 OE tOXZ DATA tDCS tDCH tOZX tAD Dual Port Write with Read tCYC tCLKH CLK tWCS WE tACS WR ADDR 0 1 tCLKL tWCH tACH 2 tDCS WR DATA tDCH RD ADDR = WR ADDR 1 tCD RD DATA 30 AT40KAL 4263B-AERO-06/03 AT40KAL/EL Dual Port Read RD ADDR 0 1 OE tOZX tAD tOXZ DATA 31 4155A-AERO-06/02 AT40KAL/EL Table 4. Pad/Pin Assignment 384 I/O GND I/O1, GCK1 (A16) I/O2 (A17) I/O3 I/O4 I/O5 (A18) I/O6 (A19) GND I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 VCC GND I/O13 I/O14 I/O15 I/O16 I/O17 I/O18 GND I/O19 I/O20 I/O21 I/O22 I/O23 I/O24 GND I/O25, FCK1 I/O26 I/O27 (A20) I/O28 (A21) VCC I/O29 I/O30 GND 10 11 12 13 14 8 9 MQFPF160 1 2 384 I/O I/O31 I/O32 I/O33 I/O34 3 4 5 6 7 I/O35 I/O36 GND VCC I/O37 I/O38 I/O39 I/O40 I/O41 I/O42 GND I/O43 I/O44 I/O45 I/O46 I/O47 (A22) I/O48 (A23) GND VCC I/O49 I/O50 I/O51 I/O52 I/O53 I/O54 GND I/O55 I/O56 I/O57 I/O58 I/O59 I/O60 VCC GND I/O61 I/O62 I/O63 I/O64 I/O65 23 24 17 18 19 20 21 22 15 16 MQFPF160 384 I/O I/O66 GND I/O67 I/O68 VCC I/O69 I/O70 I/O71 I/O72, FCK2 GND I/O73 I/O74 I/O75 I/O76 I/O77 I/O78 GND I/O79 I/O80 I/O81 I/O82 I/O83 I/O84 GND VCC I/O85 I/O86 I/O87 I/O88 I/O89 I/O90 GND I/O91 I/O92 I/O93 I/O94 I/O95 (OTS)(1) I/O96, GCK2 M1 GND M0 VCC M2 34 35 36 37 38 39 40 41 42 32 33 30 31 25 26 27 28 29 MQFPF160 32 4155A-AERO-06/02 384 I/O I/O97, GCK3 I/O98 (HDC) I/O99 I/O100 I/O101 I/O102 (LDC) GND I/O103 I/O104 I/O105 I/O106 I/O107 I/O108 VCC GND I/O109 I/O110 I/O111 I/O112 I/O113 I/O114 GND I/O115 I/O116 I/O117 I/O118 I/O119 I/O120 GND I/O121 I/O122 I/O123 I/O124 VCC I/O125 I/O126 GND I/O127 I/O128 I/O129 I/O130 I/O131 I/O132 MQFPF160 43 44 45 46 47 48 384 I/O GND VCC I/O133 I/O134 I/O135 I/O136 I/O137 I/O138 GND I/O139 I/O140 I/O141 I/O142 I/O143 (D15) I/O144 (INIT) VCC MQFPF160 384 I/O I/O165 (D12) I/O166 (D11) I/O167 I/O168 GND MQFPF160 66 67 68 69 70 56 57 I/O169 I/O170 I/O171 I/O172 I/O173 I/O174 GND 58 59 60 61 62 63 I/O175 I/O176 I/O177 I/O178 I/O179 I/O180 GND VCC I/O181 I/O182 I/O183 (D10) I/O184 (D9) 73 74 71 72 49 50 GND I/O145 (D14) I/O146 (D13) I/O147 I/O148 I/O149 I/O150 GND I/O151 I/O152 I/O153 64 65 I/O185 I/O186 GND I/O187 I/O188 I/O189 I/O190 I/O191 (D8) I/O192, GCK4 GND CON VCC RESET I/O193 (D7) I/O194, GCK5 I/O195 75 76 77 78 79 80 81 82 83 84 85 51 52 53 54 55 I/O154 I/O155 I/O156 VCC GND I/O157 I/O158 I/O159 I/O160 I/O161 I/O162 GND I/O163 I/O164 VCC 33 AT40KAL/EL 4155A-AERO-06/02 AT40KAL/EL 384 I/O I/O196 I/O197 I/O198 GND I/O199 I/O200 I/O201 I/O202 I/O203 I/O204 VCC GND I/O205 (D6) I/O206 I/O207 I/O208 I/O209 I/O210 GND I/O211 I/O212 I/O213 I/O214 I/O215 I/O216 GND I/O217 I/O218 I/O219, FCK3 I/O220 VCC I/O221 (D5) I/O222 (CS0) GND I/O223 I/O224 I/O225 I/O226 I/O227 I/O228 GND VCC 94 95 92 93 91 87 88 89 90 MQFPF160 86 384 I/O I/O229 I/O230 I/O231 I/O232 I/O233 I/O234 GND I/O235 I/O236 I/O237 I/O238 I/O239(D4) I/O240 VCC GND I/O241 (D3) I/O242 (CHECK) I/O243 I/O244 I/O245 I/O246 GND I/O247 I/O248 I/O249 I/O250 I/O251 I/O252 VCC GND I/O253 I/O254 I/O255 I/O256 I/O257 I/O258 GND I/O259 (D2) I/O260 VCC I/O261 I/O262,FCK4 I/O263 108 109 106 107 104 105 98 99 100 101 102 103 96 97 MQFPF160 384 I/O I/O264 GND I/O265 I/O266 I/O267 I/O268 I/O269 I/O270 GND I/O271 I/O272 I/O273 I/O274 I/O275 I/O276 GND VCC I/O277 (D1) I/O278 I/O279 I/O280 I/O281 I/O282 GND I/O283 I/O284 I/O285 I/O286 I/O287 (D0) I/O288, GCK6 (CSOUT) CCLK VCC TSTCLK GND I/O289 (A0) I/O290, GCK7 (A1) I/O291 I/O292 I/O293 I/O294 GND 115 116 117 118 119 120 121 122 123 113 114 111 112 110 MQFPF160 124 125 126 34 4155A-AERO-06/02 384 I/O I/O295 I/O296 I/O297 (CS1,A2) I/O298 (A3) I/O299 I/O300 VCC GND I/O301(1) I/O302 I/O303 I/O304 I/O305 I/O306 GND I/O307 I/O308 I/O309 I/O310 I/O311 I/O312 GND I/O313 I/O314 I/O315 I/O316 VCC I/O317 I/O318 GND I/O319 I/O320 I/O321 I/O322 I/O323 I/O324 GND VCC I/O325 (A4) I/O326 (A5) I/O327 I/O328 MQFPF160 384 I/O I/O329 I/O330 MQFPF160 137 138 384 I/O I/O361 I/O362 I/O363 I/O364 I/O365 I/O366 GND MQFPF160 127 128 GND I/O331 I/O332 I/O333 I/O334 I/O335 (A6) 139 140 141 142 143 144 I/O367 I/O368 I/O369 I/O370 I/O371 (A12) I/O372 (A13) GND VCC I/O373 I/O374 I/O375 I/O376 152 153 154 155 121(1) NC I/O336 (A7) GND 129 130 VCC I/O337 (A8) I/O338 (A9) I/O339 I/O340 I/O341 I/O342 GND I/O343 I/O344 145 146 I/O377 I/O378 GND I/O379 I/O380 131 132 133 I/O345 I/O346 I/O347 (A10) I/O348 (A11) VCC GND I/O349 I/O350 I/O351 I/O352 I/O353 I/O354 GND I/O355 I/O356 147 148 I/O381 I/O382 I/O383 (A14) I/O384, GCK8 (A15) VCC 156 157 158 159 160 Note: 1. Shared with TSTCLK 134 135 VCC I/O357 I/O358 I/O359 I/O360 149 150 151 136 GND 35 AT40KAL/EL 4155A-AERO-06/02 Part/Package Availability and User I/O Counts (Including Dual-function Pins) Package MQFPF 160 MQFPF 256 MQFPF 352 Note: (1) (1) AT40KAL 130 193 289 1. Contact Atmel for availabilty. Ordering Information Part Number AT40KAL040KW1M-E AT40KAL040KW1M AT40KAL040KW1MMQ Temperature Range 25C -55 to +125C -55 to +125C Quality Flow Engineering Samples Standard Mil Mil Std 883 Level B 36 AT40KAL 4263B-AERO-06/03 AT40KAL Package Drawing Multilayer Quad Flat Pack (MQFP) 160-pin 37 4263B-AERO-06/03 Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 487-2600 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131 TEL 1(408) 441-0311 FAX 1(408) 436-4314 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany TEL (49) 71-31-67-0 FAX (49) 71-31-67-2340 1150 East Cheyenne Mtn. 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No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. (c) Atmel Corporation 2003. All rights reserved. ATMEL (R), and Cache Logic(R) are registered trademarks of Atmel. FreeRAM TM and QuickChange TM are trademarks of Atmel. Concept (R), Verilog (R), and OrCAD (R), are registered trademarks of Cadence Design Systems Inc.; Mentor(R), and Veribest (R), are registered trademarks of Mentor Graphics; Exemplar TM, is a trademark of Mentor Graphics. Synario TM, is a trademark of Data I/O Corporation; Synopsis (R), is a registered trademark of Synopsis Inc.; Viewlogic TM, is a trademark of Viewlogic Systems, Inc.; Synplicity(R), is a registered trademark of Synplify, Inc. Other terms and product names may be the trademarks of others. Printed on recycled paper. 4263B-AERO-06/03 /xM |
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